Curriculum Designation: Required course for computer engineering majors. Tier II Elective course for electrical engineering majors.
Course (Catalog) Description: This course offers an overview of programmable logic devices, complex programmable logic devices, and field-programmable gate-array devices. The course offers an introduction to hardware description languages (HDLs); combinational, sequential, and finite-state machine design using HDLs; as well as top-down methodologies.
Prerequisites: EEL 3705 and EEL 3705L
- Design a combinatorial digital logic circuit using a hardware description language (HDL).
- Design a finite-state machine (FSM) using a HDL.
- Synthesize a gate-level digital logic circuit from HDL code using a gate-level cell library.
- Analyze a gate-level digital logic circuit and develop its equivalent HDL code.
- Verify the design implementation of a FSM using computer simulation.
- Determine the maximum switching frequency of a sequential circuit.
- Discuss and describe the differences and design tradeoffs between different FPLD architectures.
- Analyze contemporary issues in FPLD project design.
- Recognize the need for lifelong learning and engage in lifelong learning.
- Review of digital logic fundamentals
- Intro to VHSIC Hardware Description Language (VHDL)
- Combinatorial and synchronous logic design using VHDL.
- Introduction to Field Programmable Logic Devices (FPLDs)
- System design methodologies.
- Advanced logic design topics
Class Schedule: Three 50 minute or two 75 minute lectures per week (3 credit hours).
Contribution to Professional Component: Engineering topic: 3 credit hours
Science/Design (%): 50% / 50%
Relationship to ABET Student Outcomes: A, C, E, H, I, J, K and O(CpE)
Prepared by: Bruce A. Harvey
Revised: September 23, 2016