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ECE EEL 3705 - Digital Logic Design

Curriculum Designation: Required for electrical engineering and computer engineering majors.

Course (Catalog) Description: Fundamental topics in digital logic design, algorithms, computer organization, assembly-language programming, and computer engineering technology.

Prerequisites: COP 3014

Textbooks/Required Material: Fund of Digital Logic w/VHDL Design (w/CD), Author: Brown, Publisher: MCGRAW-HILL, Edition: 3rd, Copyright Year: 2009

Course Objectives:

  1. Calculate number conversion between different number systems
  2. Solve arithmetic equations in two - complement and interpret results regarding overflow conditions
  3. Derive digital circuits from optimized Boolean equations and compute the Boolean equations of a digital circuit
  4. Calculate and interpret costs and timing delay in combinational and sequential logic circuits
  5. Use Karnaugh maps to optimize combinatorial logic, including incompletely specified logic.
  6. Analyze and design arithmetic logic units and describe the associated control signals.
  7. Analyze characteristic tables and equations and timing diagram of latches and flip-flops.
  8. Create state diagram from sequential circuits and design sequential circuits from state diagrams.
  9. Design and verify by simulation a finite state machine satisfying given criteria.

Topics Covered:

  1. Algebra and Logic Gates
  • Truth Tables
  • Algebraic Reduction/Expansion to Standard Forms
  • Logic Devices and Implementation
  • Logic Minimization
    • Karnaugh Maps & Canonical Forms
    • Incompletely Specified & Hazard-free Design
    • Technology Mapping (NAND, NOR)
  • Number Representation, Arithmetic and Logic Circuits
    • Radix Number Conversion (Incl. Binary, Octal and Hex)
    • Binary Arithmetic (Unsigned and Signed)
    • Arithmetic-Logic Units
  • Common Combinatorial Components
    • Multiplexer, Decoder, Encoder, Converter, Comparator
  • Storage Components and Counters
    • Latches and Flip-Flops
    • Registers and Memory
    • Counters
    • Other Examples
  • Sequential Logic (State Machines)
    • State Diagram, Table and Assignment
    • Mealy and Moore Models
    • State Minimization
    • Implementation

    Class Schedule: Three 50 minute or two 75 minute lectures per week (3 credit hours).

    Contribution to Professional Component: Engineering topic: 3 credit hours

    Science/Design (%): 65% / 35%

    Relationship to ABET Program Outcomes: C and I

    Prepared by: Bruce A. Harvey

    Revised: September 23, 2016