Skip to main content

Linda DeBrunner, Ph.D.

Linda S. DeBrunner, Ph.D.
Professor
linda.debrunner@eng.famu.fsu.edu
linda.debrunner@fsu.edu
Education
  • Ph.D., Virginia Polytechnic Institute and State University, 1991
  • M.S., Virginia Polytechnic Institute and State University, 1986
  • B.E.E., Auburn University, 1984
Research Interests
  • Digital Signal Processing Hardware
  • Special Purpose Digital Implementations
  • Computer Arithmetic

Current Research Projects

  • Low Power Digital Signal Processing Implementations
  • Designing Multipliers for Digital Signal Processing Algorithms
  • Estimating Bridge Displacement

Dr. Linda DeBrunner was born in Huntsville, AL, on April 28, 1962. She received the bachelors in electrical engineering degree from Auburn University in 1984, and M.S. and Ph.D. degrees in electrical engineering from Virginia Tech in 1986 and 1991, respectively.

She joined the faculty at Florida State University in August 2006, where she serves as a Professor in Electrical and Computer Engineering at the FAMU-FSU College of Engineering. She was a faculty member at the University of Oklahoma from 1990-2006, where she left as a Professor of Electrical & Computer Engineering. Her research interests include digital signal processing hardware, special-purpose digital systems and computer arithmetic.

DeBrunner has received over $6 million in external funding since 1990. Funding sources include the National Science Foundation, the Office of Naval Research, the Federal Highway Administration, as well as state–based funding sources and private companies. She has published more than 50 refereed papers.

DeBrunner has been twice named Favorite Professor in Electrical and Computer Engineering. She is an associate editor for the Journal of Circuits, Systems, and Computers and serves on the steering committee for the Asilomar Conference on Signals, Systems, and Computers. She also serves on the IEEE Circuits and Systems Society Technical Committee for Digital Signal Processing, as well as the Technical Committee for VLSI Systems & Applications. She is a senior member of the Institute of Electrical and Electronics Engineers.

Publications
  1. Mookherjee, Soumak; DeBrunner, Linda S.; DeBrunner, Victor, "A hardware efficient technique for linear convolution of finite length sequences," Signals, Systems and Computers, 2013 Asilomar Conference on, vol., no., pp.515,519, 3-6 Nov. 2013
    doi: 10.1109/ACSSC.2013.6810331
    keywords: {Algorithm design and analysis;Clocks;Convolution;Hardware;MATLAB; Registers;Throughput;Convolution;DSP;FFT;HOT;Implementation}
  2. Rui Guo; DeBrunner, L.S., "A novel fast canonical-signed-digit conversion technique for multiplication,"Acoustics, Speech and Signal Processing (ICASSP), 2011 IEEE International Conference on, vol., no., pp.1637,1640, 22-27 May 2011
    doi: 10.1109/ICASSP.2011.5946812
    keywords: {digital arithmetic;multiplying circuits;CSD conversion;fast canonical signed digit conversion technique;fast multiplication;least significant bit;most significant bit;multiplier;unsigned binary number conversion;Computers;Delay; Digital signal processing;Hardware;Logic gates;Propagation delay;Booth's Recoding;canonical-signed-digit (CSD);minimum-signed-digit (MSD);redundant number representation}
  3. Johansson, K.; Gustafsson, O.; DeBrunner, L.S.; Wanhammar, L., "Minimum adder depth multiple constant multiplication algorithm for low power FIR filters,"Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, vol., no., pp.1439,1442, 15-18 May 2011
    doi: 10.1109/ISCAS.2011.5937844
    keywords: {FIR filters;adders;low-power electronics;multiplying circuits;low power FIR filters;minimum adder depth algorithm;multiple constant multiplication;multiplier coefficients;Adders;Algorithm design and analysis;Complexity theory;Finite impulse response filter;Power demand;Signal processing algorithms;Sparse matrices}
  4. Kandula, V.; DeBrunner, L.; DeBrunner, V.; Rambo-Roddenberry, M., "Estimating bridge displacement from acceleration using modal analysis and the minimum description length principle,"Signals, Systems and Computers (ASILOMAR), 2011 Conference Record of the Forty Fifth Asilomar Conference on, vol., no., pp.1057,1061, 6-9 Nov. 2011
    doi: 10.1109/ACSSC.2011.6190174
    keywords: {acceleration;acceleration measurement;accelerometers;noise removal; condition monitoring;bridges (structures);modal analysis;noise abatement;structural engineering; accelerometers;bridge displacement estimation;laser systems; displacement transducers; dynamic displacement estimation;load rating;minimum-description length principle;modal analysis;moving-vehicle loads;static displacement; stationary reference point;structural health evaluation; Acceleration;Accelerometers; Bridges;Displacement measurement;steel beam acceleration;Vehicle dynamics;Matrix decomposition;Noise}
  5. Rui Guo; DeBrunner, L.S., "Two High-Performance Adaptive Filter Implementation Schemes Using Distributed Arithmetic,"Circuits and Systems II: Express Briefs, IEEE Transactions on, vol.58, no.9, pp.600,604, Sept. 2011
    doi: 10.1109/TCSII.2011.2161168
    keywords: {FIR filters;adaptive filters;computational complexity;distributed arithmetic;least mean squares methods;table lookup;bit-level architectures; computation complexity;digital filters;distributed arithmetic;finite-impulse response filters;high-performance adaptive filter;least-mean-square adaptation;lookup tables; mean square error;vector-vector multiplication;Digital signal processing;Encoding; Finite impulse response filter;Least squares approximation;Read only memory;Speech processing;Table lookup;Adaptive filter;distributed arithmetic (DA);finite-impluse response (FIR);least mean square (LMS);lookup table (LUT); multiply accumulate (MAC);offset-binary coding (OBC)}