New Software: Better Results?
Altera recommends to use Quartus with any new design. Max+plus
II support seemed to be terminated in the near future. To simplify the
conversion Quartus II has (starting with version 4) now a interface “Convert
MAX+PLUS II Project” in the File menu. It generates all Quartus
setting and worked without problem for all 30+ examples.
The conversion of Max+plus II simulation file (*.scf) to the embedded Quartus simulator requires some more effort: First you need to use again the Max+plus II software to generate a “table file.” Use the “Create Table File…” function in the File menu. This table file can be read by Quartus, but not the original *.scf files!
The key question is now: How good are the synthesis results with Quartus when compared with MaxPlusII. To evaluate this questions the 30+ design examples are compiled with Quartus.
The table below shows the Quartus II web Edition Ver. 4 synthesis results of the examples from the book DSP with FPGAs by Dr. Uwe Meyer-Baese when compared with the Max+plus II results. We see that the overall synthesis results when compared LCs and Registered Performance under the “Total” entry. The main problem with this Quartus version is that LUT and flip-flop are not combined in a single LE most of the time for 10K devices. Better results are achieved for APEX (APEX20K200EFC484-2X included on Altera’s Nios development boards) and Stratix (In cluded in Altera’s DSP development boards) devices. The “Auto Packed Register” synthesis option set to “Minimize Area” does not seemed to have an positive effect on 10K devices.
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Max 10.2 versus Quartus II
web Ver. 4 |
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VHDL DEVICE=EPF10K70RC240-4 |
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Design |
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LCs |
Gain % |
MHz |
Gain % |
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add_1p |
85 |
-69.41 |
63.29 |
0.00 |
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add_2p |
158 |
-63.29 |
58.82 |
-7.06 |
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add_3p |
254 |
-58.66 |
57.47 |
-5.74 |
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ammod |
339 |
-17.70 |
27.70 |
-2.77 |
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bfproc |
545 |
-2.57 |
16.56 |
22.12 |
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ccmul |
386 |
27.72 |
0.00 |
0.00 |
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cic3r32 |
526 |
-23.76 |
40.00 |
0.00 |
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cic3s32 |
422 |
-43.60 |
44.64 |
0.00 |
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cordic |
315 |
-22.54 |
27.25 |
-31.33 |
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dafsm |
45 |
-17.78 |
65.79 |
17.13 |
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dapara |
47 |
-17.02 |
37.45 |
17.62 |
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darom |
42 |
-19.05 |
33.44 |
19.43 |
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dasign |
59 |
10.17 |
42.74 |
27.81 |
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db4latti |
488 |
-32.17 |
6.23 |
-86.23 |
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db4poly |
353 |
-41.08 |
7.70 |
-90.22 |
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div_aegp |
364 |
28.85 |
18.80 |
28.86 |
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div_res |
137 |
30.66 |
45.25 |
20.38 |
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example |
40 |
-37.50 |
64.52 |
-48.38 |
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fir6dlms |
595 |
10.59 |
33.22 |
41.91 |
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fir_gen |
794 |
12.34 |
40.82 |
-2.02 |
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fir_lms |
497 |
23.14 |
12.5 |
38.89 |
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fir_srg |
142 |
-31.69 |
18.62 |
6.70 |
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fun_text |
64 |
-50.00 |
38.46 |
-29.61 |
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iir |
90 |
-65.56 |
29.41 |
-31.46 |
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iir_par |
448 |
-52.01 |
7.04 |
-77.54 |
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iir_pipe |
193 |
-66.84 |
34.72 |
-30.21 |
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lfsr |
6 |
0.00 |
125 |
175.03 |
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lfsr6s3 |
6 |
0.00 |
125 |
185.06 |
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mul_ser |
120 |
-4.17 |
40.98 |
-0.41 |
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rader7 |
806 |
-39.70 |
13.61 |
-40.93 |
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Total |
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-18.8 |
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3.90 |
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Max 10.2 versus Altera web
Quartus II Vers. 4 |
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VHDL
Device=APEX20K200EFC484-2X |
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Design |
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LCs |
Gain % |
MHz |
Gain % |
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add_1p |
63 |
-58.73 |
175.84 |
177.83 |
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add_2p |
119 |
-51.26 |
175.59 |
177.44 |
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add_3p |
192 |
-45.31 |
159.59 |
161.75 |
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ammod |
260 |
7.31 |
74.79 |
162.51 |
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bfproc |
520 |
2.12 |
36.45 |
168.81 |
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ccmul |
375 |
31.47 |
0.00 |
0.00 |
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cic3r32 |
370 |
8.38 |
100.39 |
150.98 |
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cic3s32 |
303 |
-21.45 |
74.95 |
67.90 |
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cordic |
230 |
6.09 |
67.69 |
70.59 |
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dafsm |
35 |
5.71 |
217.01 |
286.35 |
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dapara |
44 |
-11.36 |
101.16 |
217.71 |
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darom |
32 |
6.25 |
110.63 |
295.11 |
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dasign |
59 |
10.17 |
106.32 |
217.94 |
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db4latti |
417 |
-20.62 |
16.77 |
-62.93 |
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db4poly |
197 |
5.58 |
46.10 |
-41.45 |
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div_aegp |
368 |
27.45 |
39.34 |
169.64 |
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div_res |
134 |
33.58 |
102.93 |
173.82 |
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example |
24 |
4.17 |
233.64 |
86.91 |
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fir6dlms |
529 |
24.39 |
72.63 |
210.25 |
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fir_gen |
724 |
23.20 |
118.26 |
183.87 |
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fir_lms |
477 |
28.30 |
25.24 |
180.44 |
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fir_srg |
136 |
-28.68 |
47.63 |
172.95 |
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fun_text |
32 |
0.00 |
113.38 |
107.50 |
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iir |
75 |
-58.67 |
74.09 |
72.66 |
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iir_par |
279 |
-22.94 |
59.55 |
90.01 |
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iir_pipe |
133 |
-51.88 |
90.11 |
81.13 |
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lfsr |
6 |
0.00 |
233.64 |
414.06 |
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lfsr6s3 |
6 |
0.00 |
233.64 |
432.82 |
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mul_ser |
230 |
-50.00 |
117.22 |
184.86 |
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rader7 |
489 |
-0.61 |
67.38 |
192.45 |
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Total |
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-4.6 |
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160.13 |
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Max 10.2 versus Altera web
Quartus II Vers. 4 |
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VHDL Device=Stratix
EP1S10F484C5 |
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Design |
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9x9 mul. |
LCs |
Gain % |
MHz |
Gain % |
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add_1p |
0 |
63 |
-58.73 |
328.52 |
419.07 |
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add_2p |
0 |
119 |
-51.26 |
326.69 |
416.18 |
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add_3p |
0 |
192 |
-45.31 |
325.41 |
433.72 |
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ammod |
0 |
210 |
32.86 |
215.56 |
656.62 |
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bfproc |
3 |
159 |
233.96 |
69.17 |
410.10 |
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ccmul |
3 |
43 |
1046.5 |
0.00 |
0.00 |
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cic3r32 |
0 |
355 |
12.96 |
258.40 |
546.00 |
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cic3s32 |
0 |
276 |
-13.77 |
187.55 |
320.14 |
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cordic |
0 |
160 |
52.50 |
200.52 |
405.34 |
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dafsm |
0 |
29 |
27.59 |
422.12 |
651.50 |
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dapara |
0 |
30 |
30.00 |
207.77 |
552.54 |
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darom |
0 |
26 |
30.77 |
232.50 |
730.36 |
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dasign |
0 |
48 |
35.42 |
243.72 |
628.83 |
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db4latti |
0 |
412 |
-19.66 |
36.67 |
-18.94 |
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db4poly |
0 |
190 |
9.47 |
145.90 |
85.29 |
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div_aegp |
4 |
62 |
656.45 |
111.10 |
661.48 |
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div_res |
0 |
133 |
34.59 |
270.20 |
618.81 |
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example |
0 |
24 |
4.17 |
422.12 |
237.70 |
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fir6dlms |
4 |
84 |
683.33 |
155.74 |
565.27 |
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fir_gen |
4 |
120 |
643.33 |
273.75 |
557.11 |
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fir_lms |
4 |
66 |
827.27 |
61.38 |
582.00 |
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fir_srg |
0 |
132 |
-26.52 |
91.77 |
425.90 |
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fun_text |
0 |
32 |
0.00 |
290.87 |
432.34 |
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iir |
0 |
75 |
-58.67 |
159.34 |
271.34 |
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iir_par |
0 |
277 |
-22.38 |
90.55 |
188.93 |
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iir_pipe |
0 |
132 |
-51.52 |
210.04 |
322.19 |
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lfsr |
0 |
6 |
0.00 |
422.12 |
828.76 |
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lfsr6s3 |
0 |
6 |
0.00 |
422.12 |
862.65 |
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mul_ser |
0 |
117 |
-1.71 |
284.74 |
591.96 |
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rader7 |
0 |
450 |
8.00 |
142.55 |
518.71 |
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Total |
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135.9 |
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463.40 |