New Software: Better Results?

 

Altera recommends to use Quartus with any new design. Max+plus II support seemed to be terminated in the near future. To simplify the conversion Quartus II has (starting with version 4) now a interface “Convert MAX+PLUS II Project” in the File menu. It generates all Quartus setting and worked without problem for all 30+ examples.

The conversion of Max+plus II simulation file (*.scf) to the embedded Quartus simulator requires some more effort: First you need to use again the Max+plus II software to generate a “table file.” Use the “Create Table File…” function in the File menu. This table file can be read by Quartus, but not the original *.scf files!

The key question is now: How good are the synthesis results with Quartus when compared with MaxPlusII. To evaluate this questions the 30+ design examples are compiled with Quartus.

 

The table below shows the Quartus II web Edition Ver. 4 synthesis results of the examples from the book DSP with FPGAs by Dr. Uwe Meyer-Baese when compared with the Max+plus II results. We see that the overall synthesis results when compared LCs and Registered Performance under the “Total” entry. The main problem with this Quartus version is that LUT and flip-flop are not combined in a single LE most of the time for 10K devices. Better results are achieved for APEX (APEX20K200EFC484-2X included on Altera’s Nios development boards) and Stratix (In cluded in Altera’s DSP development boards) devices. The “Auto Packed Register” synthesis option set to “Minimize Area” does not seemed to have an positive effect on 10K devices.

 

 

Max 9.23 versus Altera Quartus II Version 4 web

VHDL Device= FLEX10K20RC240-4

Design

 

 

 

 

 

LCs

Gain %

MHz

Gain %

add_1p

85

-69.41

73.53

-24.26

add_2p

158

-63.29

68.49

-27.39

add_3p

254

-58.66

67.57

-26.35

ammod

339

-17.70

33.11

-18.55

bfproc

545

-2.20

18.94

3.05

ccmul

386

27.72

0.00

0.00

cic3r32

495

-32.93

40.32

4.84

cic3s32

423

-52.96

34.36

-17.52

cordic

315

-18.73

34.60

-20.40

dafsm

45.00

-17.78

68.97

11.75

dapara

47.00

-17.02

42.74

1.30

darom

42.00

-19.05

34.84

8.03

dasign

59.00

10.17

49.26

16.76

db4latti

488.00

-31.56

7.31

-87.94

db4poly

353.00

-41.08

9.14

-89.94

example

40.00

-37.50

74.07

-40.74

fir_gen

794

12.09

47.39

1.43

fir_srg

142

-31.69

21.14

8.24

fun_text

64

-50.00

42.55

-28.09

iir

90

-65.56

34.13

-38.90

iir_par

448

-52.46

8.59

-85.22

iir_pipe

193

-66.84

40.16

-45.38

lfsr

6

0.00

125

25.00

lfsr6s3

6

0.00

125

31.26

mul_ser

120

-7.50

42.74

-6.82

rader7

806

-38.71

16.72

-44.15

Total

 

-25.9

 

-18.85

 

 

Max 9.23 versus Altera web Quartus II Vers. 4

VHDL Device=APEX20K200EFC484-2X

Design

 

 

 

 

 

LCs

Gain %

MHz

Gain %

add_1p

63

-58.73

175.84

81.13

add_2p

119

-51.26

175.59

86.14

add_3p

192

-45.31

159.59

73.96

ammod

260

7.31

74.79

83.99

bfproc

520

2.50

36.45

98.31

ccmul

375

31.47

0.00

0.00

cic3r32

370

-10.27

100.39

161.02

cic3s32

303

-34.32

74.95

79.91

cordic

230

11.30

67.69

55.72

dafsm

35.00

5.71

217.01

251.60

dapara

44.00

-11.36

101.16

139.77

darom

32.00

6.25

110.63

243.04

dasign

59.00

10.17

106.32

152.00

db4latti

417.00

-19.90

16.77

-72.33

db4poly

197.00

5.58

46.10

-49.28

example

24.00

4.17

233.64

86.91

fir_gen

724

22.93

118.26

153.13

fir_srg

136

-28.68

47.63

143.88

fun_text

32

0.00

113.38

91.62

iir

75

-58.67

74.09

32.64

iir_par

279

-23.66

59.55

2.44

iir_pipe

133

-51.88

90.11

22.57

lfsr

6

0.00

233.64

133.64

lfsr6s3

6

0.00

233.64

145.34

mul_ser

230

-51.74

117.22

155.55

rader7

489

1.02

67.38

125.05

Total

 

-9.3

 

82.59

 

 

Max 9.23 versus Altera web Quartus II Vers. 4

 

VHDL Device=Stratix EP1S10F484C5

 

Design

 

 

 

 

 

 

9x9 mul.

LCs

Gain %

MHz

Gain %

add_1p

0

63

-58.73

328.52

238.40

add_2p

0

119

-51.26

326.69

246.33

add_3p

0

192

-45.31

325.41

254.71

ammod

0

210

32.86

215.56

430.28

bfproc

3

159

235.22

69.17

276.33

ccmul

3

43

1046.5

0.00

0.00

cic3r32

0

355

-6.48

258.40

571.87

cic3s32

0

276

-27.90

187.55

350.19

cordic

0

160

60.00

200.52

361.28

dafsm

0

29

27.59

422.12

583.93

dapara

0

30

30.00

207.77

392.46

darom

0

26

30.77

232.50

620.93

dasign

0

48

35.42

243.72

477.67

db4latti

0

412

-18.93

36.67

-39.49

db4poly

0

190

9.47

145.90

60.51

example

0

24

4.17

422.12

237.70

fir_gen

4

120

641.67

273.75

485.94

fir_srg

0

66

46.97

91.77

369.89

fun_text

0

32

0.00

290.87

391.58

iir

0

75

-58.67

159.34

185.25

iir_par

0

277

-23.10

90.55

55.77

iir_pipe

0

132

-51.52

210.04

185.69

lfsr

0

6

0.00

422.12

322.12

lfsr6s3

0

6

0.00

422.12

343.26

mul_ser

0

117

-5.13

284.74

520.75

rader7

0

450

9.78

142.55

376.12

Total

 

 

64.1

 

276.65